Integrated circuits are becoming increasingly more complex as more core devices and supporting logic are integrated onto a single chip. This is driven, in part, from the need to provide increased functionality in less space, with lower power consumption and with higher bandwidths. These product performance requirements force integrated circuit designers to populate a single chip with several devices which may include controllers, memory blocks, processors, and various input/output (I/O) interfaces to provide a complex integrated circuit.
As an example, improvements in microprocessor performance has resulted in data transfer bandwidths that typically outpace I/O transfer rates. In the telecommunications industry, for example, high speed telecommunications data is converted into multiple low-speed T1 data paths for transmission and then reconverted to the high-speed data at the receiver. As another example, analogue signals are routinely converted to a digital signal, transmitted, and then reconverted back to the analog signal.
Similarly, parallel data I/O bus bottlenecks result in performance compromises in peripheral and network interfaces, and accordingly have spurred the development of high-speed serial transfer methods. Unlike conventional protocols where data is transferred over multiple conducting traces or wires, parallel data is converted into a high-speed, serial data stream. The serial data stream is typically converted back to parallel data be a deserializer at a receiving peripheral device for application with the particular logic in that device. Integration of such I/O interfaces as part of a complex integrated circuit on a single chip is consistent with proximally locating the serializer/deserializer I/O with the devices that are either transmitting or receiving the data, thus avoiding I/O bus bandwidth limitations and enabling higher data transfer rates. The integration of increasing numbers of functional devices onto a single chip and the resulting complex interconnectivity requirements of these devices with other devices on and off the chip has resulted in the integration of high-speed serializer/deserializer I/O interface cores or macrocells onto the chip containing the customers logic.
High levels of device integration onto a single chip, while reducing the chip count on a board, will increase the unit cost of the integrated circuit. This is principally due to lower manufacturing yields resulting from the increased process complexities associated with the manufacture of such highly integrated devices, as well as the yield impact attendant with the additional process steps required to fabricate these chips. Accordingly, it is well known that the likelihood of manufacturing defects increases as chip complexity increases. Core device tolerances become increasingly critical as the devices are packed closer together and are required to operate and interact at higher bandwidths. Deviation from these tolerances can cause defects in the chips resulting in lower process yields, increased screening of finished goods, resulting in higher per unit costs. Also, the additional process steps associated with the fabrication of these highly integrated circuits provide further opportunities for defects and thus increased cost due to lower manufacturing yields.
The high cost of manufacturing these complex integrated circuits makes it desirable, therefore, to identify product defects as early in the manufacturing process as possible, thus avoiding the expense of further processing an otherwise defective chip. Also, early manufacturing rejection of defective parts reduces the amount of screening required of the finished product. Accordingly, where an I/O interface is incorporated as a core device on an integrated circuit, it is desirable to test the I/O interface during the manufacture, or as shortly thereafter as possible, of the integrated circuit to determine if the I/O interface is operating to specification before additional time and money are expended to complete the fabrication of what might otherwise be a defective device, or to avoid costs associated with installation of a defective device onto a board.
Currently there are no commercially available testers capable of testing an embedded, high-speed I/O interface at the I/O interface design limits. Current testing devices and hardware are limited to data transfer rates of up to about 500 Mb/sec. Consequently, serializer/deserializer I/O interfaces capable of data transfer rates exceeding 500 Mb/sec cannot be tested to the limits of the I/O interface's data transfer rate performance specification on testers that are commercially available today. To compound the problem, merely testing the I/O interface at a commercially available tester's highest data transfer rate is not an acceptable solution because many high-speed I/O interface devices are incapable of operating at the relatively lower speeds limiting these testers. Further, even if the device could be tested at these lower data rates, such a test is not indicative of the integrity or quality of the I/O interface device since it is not being tested at its full operating data transfer rate. Accordingly, testing of embedded I/O interface devices using commercially available testers is not possible, and confirmation of the operability and performance of the embedded I/O is not possible until the chip on which the I/O is assembled is at least assembled at the board level, at which time any defect detected becomes more core costly to repair or replace.
Currently, wrapback testing of high-speed serializer/deserializer I/O interfaces cannot be performed within the I/O macrocell. Such testing may only be performed on nonintegrated I/O components where interconnectivity between the nonintegrated components permit such testing, or is performed in combination with either other chips on a completed card or as part of the entire communications system in which the card is component (such testing of components external to the serializer/deserializer I/O interface is more appropriately termed "loopback" testing). With this method of testing, it cannot be determined which chip on a card or which device on a chip is defective in the event a fault is detected. As a result, either the entire board is discarded or further testing is required in order to identify the defective board component so that it might be replaced. Such fault testing is not optimal in the sense that significant cost can be avoided if it can be determined that the I/O interface is defective early in the manufacture of the component chip containing the I/O interface core, or before assembly of that chip onto a board.
Accordingly, there is a need for on-chip diagnostics systems and methods for core I/O interface devices, including serializer/deserializer I/O interfaces, inverse multiplexer telecommunications interfaces, and analog/digital interfaces so that defects may be detected early during the manufacturing process.
Kovach et al., U.S. Pat. No. 5,043,931, teaches a wrap back diagnostic capability on analog-to-digital conversion systems, for example audio digitizing capture and playback adapter boards or cards. They teach a connector system on an I/O card having a first state wherein digital-to-analog converter (DAC) outputs are automatically, internal to the card, routed to corresponding analog-to-digital converter (ADC) inputs thereby closing a wrap loop whereupon automated DAC to ADC loop tests are performed. They also teach a second switching state which is provided automatically upon insertion of connector plugs (such as miniature audio plugs) into the connector system whereby the loop is broken and the DAC outputs and ADC inputs are made available externally to respective output and input connectors for normal operation of the card. Their system will detect board-level I/O faults only after the component chips have been fabricated and assembled onto the card. Their system does not provide for detecting defects in the I/O interface or other integrated core devices, thus precluding wrapback testing of the during manufacture of the I/O chip, or of an embedded I/O core in an integrated circuit prior to its assembly onto a circuit board.
Marshall, U.S. Pat. No. 5,274,668, teaches using the demodulator circuit of his invention as a component in a signal processing circuit. The signal processing circuit is shown as consisting of several integrated circuits including a digital transmitter-receiver integrated circuit as an additional board component. The digital transmitter-receiver integrated circuit is shown as having an internal feedback loop going from the output of the tansmitter to the input of the receiver. Data looped back from the transmitter is compared off-chip in a processor circuit with the original data. This test is unsuitable for the early detection of defects in the manufacturing process in a core I/O interface of an integrated cirecuit. As taught, this test scheme requires two separate integrated circuits. The signal comparison in this circuit is performed by a different, separate integrated circuit (the "processor") thus making possible the loop-back test only after the board has been assembled. Consequently, early manufacturing loop-back testing of the digital transmitter-receiver core cannot be performed during the manufacturing of the transmitter-receiver core since the additional processor integrated is required to perform the test.
Other wrap-back and loop-back diagnostic systems are typified by Barton et al., U.S. Pat. No. 5,343,4611. They describe a facility-level loop-back test, diagnostic and maintenance system having a digital transmission facility, transmission medium, and at least one microprocessor-based, full duplex facility loop-back diagnostics interface located at predetermined end-user locations within their system. Their system is intended to fault test an entire system, such as a local area network, wide area network, or telephone system. Their system fault testing will not identify faults up to the I/O interface circuit. A failed circuit within the I/O interface circuit will not be detected by this system or any other system wherein the loop-back or wrap back is performed off-chip and includes external elements such as transmission lines, wires, fiber-optic cable, other logic, and the like. In the event a fault was detected, these external elements would introduce uncertainty as to which element may have failed.
Other background art is directed to loop-back and wrap-back testing schemes of data communication systems whereby such testing does not interfere with the availability of the communications system. Casady et al., U.S. Pat. No. 4,908,819, is directed to a an integrated data voice multiplxer (IDVM) capable of simultaneously supporting loop-back and communication handshake protocols with no performance degradation. He shows a wide-area like network wherein data is transmitted using frequency shift keyed modulation of two or more carrier signals. The presence or absence of crrier signals is used to indicate a loop-back state. Their invention is directed to a completed, installed macro-system, and improves over Barton et al and the like, by providing for loop-back testing without interfering with the availability of the system.
There is a need to provide an on-chip self-test wrap-back test system in an I/O interface core of an integrated circuit to provide a means for fault testing the I/O interface circuit so that the defective I/O interface circuit may be identified as early as possible in the manufacturing process. Further, a wrap-back test within the I/O interface core of an integrated circuit is needed in order to provide resolution sufficient to identify an operational fault with the I/O interface in the event a system fault is determined to have occurred.